A semiconductor wafer or substrate can be made with a variety of base substrate materials, such as silicon (Si), germanium, aluminum phosphide, aluminum arsenide, gallium arsenide (GaAs), gallium nitride (GaN), aluminum gallium nitride over gallium nitride (AlGaN/GaN), indium phosphide, silicon carbide (SiC), or other bulk material for structural support. A plurality of semiconductor die is formed on the wafer separated by a non-active, inter-die substrate area or saw street. The saw street provides cutting areas to singulate the semiconductor wafer into individual semiconductor die.
The semiconductor die may contain read-only-memory (ROM) implemented using a one-time programmable (OTP) fuse to permanently store data. ROM holds information such as firmware, encryption keys, identification code, parametric trim information, or other configuration or local fixed data for the semiconductor die. An OTP fuse as formed on a semiconductor die can be programmed by driving relatively high electrical currents through the fuse. A programmed fuse reads as a relatively high electrical resistance, while a fuse that has not been programmed reads as a relatively low electrical resistance. Programmed and unprogrammed fuses are read by driving a lower electrical current through the fuse to measure a voltage level indicative of the fuse resistance, and comparing the voltage level against a threshold value. The lower electrical current is used to read the fuses without affecting their resistance. Unprogrammed fuses are interpreted as a first logic state, e.g., logic zero, while programmed fuses are interpreted as a second logic state, e.g., logic one.
In the prior art, an OTP fuse is commonly formed by a polysilicon layer disposed laterally (horizontally) across a surface of the semiconductor die, in a plane parallel to the active surface. A relatively thin silicide layer is formed on the lateral polysilicon layer. The polysilicon layer is doped such that it has a high electrical resistance relative to the overlying silicide layer. The large electric current used for programming an OTP fuse is initially carried mostly by the silicide layer, which causes the silicide layer to heat to a temperature that melts and diffuses a portion of the silicide material into the polysilicon. The current is then carried predominately by the fuse body as the silicide and dopant atoms drift or migrate to one end of the fuse. Once the silicide has sufficiently diffused and drifted to one end, polycrystalline or amorphous silicon remains in the body of the fuse. The electrical resistance of the programmed fuse is therefore approximately equivalent to the electrical resistance through the amorphous silicon body, which is significantly higher than an unprogrammed fuse that includes a complete low resistance path of silicide through the fuse.
The lateral OTP fuse takes up significant space on the semiconductor die due to its planar orientation with respect to the die surface. The driver circuit for directing the programming current through the OTP fuse also takes up considerable space. Many prior art OTP implementations use driver transistors formed in spaces laterally offset from the fuses themselves. In area-sensitive applications, which include most semiconductor die, it is desirable to minimize the space allocation for the OTP fuse and associated programming circuits. The die area allocation for OTP fuses becomes particularly problematic for applications with large OTP memory requirements. A large die may be needed for a number of lateral OTP fuses, which adds cost.